Semiconductor chips face constant development aimed at increasing the performance of the circuits supported by the chips while decreasing the overall physical size of the chips. Physical limitations like power dissipation in integrated circuits (IC's) and the process technology for fabricating IC's on an ever smaller scale have recently encouraged vertically stacking a plurality of chips instead of further increasing the lateral device density to enhance performance.
Semiconductor chips which are to be vertically stacked may be fabricated to include through silicon vias to establish electrical connections between the vertically stacked semiconductor chips. The through silicon vias are typically high aspect ratio holes in the semiconductor chips that are filled or plated with a metal or conductor to electrically connect two or more layers of circuit elements.
Semiconductor chips may also be provided with a multi-level rewiring structure which typically includes a number of electrically conductive and dielectric layers fabricated on the front side of the semiconductor chip. The multi-level rewiring structure enables the integrated circuit structures fabricated in the semiconductor body to be connected to contact pads on the outermost surface of the chip. Uniform coverage of the side walls of vias extending between the different layers of the multi-layer metallization is also desirable.
Vias both as part of a multi-level rewiring structure as well as through silicon vias extending through the body of the semiconductor chip may have an aspect ratio of at least 5:1, or at least 10:1 and possibly even at least 20:1 or more in the future. Aspect ratio is used to describe the ratio of the height of the via to its width. However, high aspect ratios make it difficult to cover the side walls of the via with a layer of material which has a uniform thickness over the side walls.
Additionally, the use of copper in place of aluminum for the metallization providing the rewiring structures on the surfaces of the semiconductor chips as well as for through silicon vias may enable additional improvements in heat dissipation since copper has a resistivity which is only about half that of aluminium. However, copper has the disadvantage that it diffuses into silicon and, if this occurs, can damage the integrated circuits of the chip and impair its performance.
U.S. Pat. No. 6,911,124 B2 and U.S. Pat. No. 7,253,109 B2 disclose a structure including a lower Ta or TaNx layer, a middle TaN seed layer and an upper Ta layer which aims to prevent the diffusion of copper into the silicon substrate.
However, tantalum metal has two crystalline phases: a low resistivity (15-60 micro-ohm-cm) alpha (body centered cubic) phase and a higher resistivity (150-210 micro-ohm-cm) beta (tetragonal) phase. The alpha phase is desired over the beta phase for use as a barrier for electronic applications due to its lower resistivity. However, the deposition conditions have to be carefully controlled in order to avoid the formation of the higher resistivity beta phase.
Therefore, it is desirable to provide a metallization structure for a semiconductor chip which can be reliably deposited with a low resistivity and which is suitable for use with copper interconnects.